When designing a circuit, many engineers will not forget to add a variety of protection circuits, especially in particularly vulnerable I/O ports. Perhaps you didn't pay attention to the "high-voltage pulse" before, and here we give everyone a trick today: how to avoid circuit design pits.
In the product design process, we often pay more attention to the appearance, function, and performance of the product, but do not pay enough attention to some details. In many cases, it is these seemingly inconspicuous details that cause major problems for the product.
For example, when designing the P800isp power supply circuit, we focused on the hard indicators such as voltage amplitude, ripple, and load regulation, and we ignored the situation at power-on. When we programmed and debugged the chip on the target board provided by the customer with P800isp, we found a strange phenomenon:
l When the programmer is powered on and then connected to the target board, the target chip can be erased, programmed, and verified.
l When the programmer is powered on after the target board is connected, any operation on the target chip will fail;
l When the programmer is powered on after the target board is connected, the programming will fail if the target board is powered on first, then connected, or first connected and then powered on.
Colleagues tried their own way to touch the programmed failed chip by hand, and their fingers were all hot. With a multimeter, it was found that the chip's power supply pin and ground, which failed to program, had been short-circuited. Measure the voltage of the programming power supply. Therefore, according to our experience, it is presumed that there is a possibility that the programming power supply abnormally high-voltage output will breakdown the target chip when the programmer is powered on. Using an oscilloscope to capture the waveform of the programming power supply Vout at the instant of the programmer confirmed our conjecture.
As shown in Fig. 1, when the programmer is powered on, the programming power supply Vout has a pulse output of up to 20.4V and a duration of up to 150ms to the target chip. The 3.3V target chip that supplies power is obviously unable to withstand such high voltage pulses.
Figure 1 The abnormal output of Vout at power up
It can be seen from the schematic diagram of the Vout power supply circuit in FIG. 2 that Vout is controlled by Vout_EN, and the low level enables Vout output. Vout_EN is pulled up to a 3.3V high level. When the power is turned on, the Vout output should be disabled by default. How can this high-voltage pulse output be output?
Figure 2 Vout power circuit schematic
It can be seen from Figure 1 that after Vout outputs 20.4V for nearly 30ms, Vout_EN is pulled high to disable the Vout output, after which Vout gradually decreases to 0V. Why Vout_EN is more effective than Vout lag 30ms instead of being powered on?
Let's look at Figure 3 below. Since 3.3V is converted from 24V to 5V, it takes a certain amount of time to generate 3.3V. The corresponding Vout_EN also takes some time to become effective. It is because of this time difference that Vout can output a high voltage pulse of 20.4V.
Figure 4 3.3V power supply
To solve the problem of the enable signal lag, the best solution is to use the input power Vin as the enable level. When the input power is turned on, the output of Vout can be disabled directly. A level-shifting circuit is added between the Vout_EN and the Vin enable level so that the Vout_EN level of 3.3V can normally control the output of Vout after the program is running. After improvement, the high-voltage pulses at the moment of power-up were perfectly eliminated.
Figure 5 Improved Vout Power Circuit
Therefore, in the design process of the product, it is not allowed to neglect the slightest and have the spirit of ingenuity in order to create a quality product.
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