IBM and partners successfully developed a 7-nanometer test chip, continuing Moore's Law, breaking the bottleneck in the semiconductor industry. For IBM, the subsequent development of 7-nanometer process technology will affect the blueprint for its Power series of processors.
According to the The Platform website, the 7nm process chip incorporates many new technologies that have not yet been tested for mass production. Partners such as IBM and GlobalFoundries, Samsung Electronics, Other chips did not put timetable.
IBM this time used silicon germanium to make a fraction of the transistors, thereby reducing the power consumption needed for fast switching while improving circuit performance, with the circuitry being etched using Extreme Ultra Violet (EUV) lithography.
IBM research shows that the most advanced technology can produce 10-nanometer chips, but the use of silicon germanium for the production of transistor channels and EUV lithography can reduce the size of the transistor half, while also being able to improve the circuit power efficiency of 50%. However, the EUV is particularly sensitive to vibrations and the manufacturing process is very sophisticated, making it difficult to produce in volume and at a very high price.
IBM said the 7-nanometer process will allow nails-sized server chips to hold 20 billion transistors, nearly four times as much as Power8 chips, and the chip size should be much smaller than the Power8. In contrast, Intel's upcoming 72-core Knights Landing Xeon Phi processor currently has only about 8 billion transistors.
On the server side, Intel has adopted the 14nm process for the Xeon processor's Broadwell architecture family and is aiming to mass-produce the Skylake desktop and notebook processors using the same 14nm process by the end of 2015. Skylake Xeon processor is expected to be available in 2017.
IBM battles Xeon's processors with Power chips and keeps pace with competitor Intel by partnering with other businesses to strengthen other companies' investment confidence in the Power line.
IBM Power7 processor using 45-nanometer process, upgrade to 8-core chip, the clock speed is between 2.4 ~ 4.25GHz. In addition, each chip has 32MB of DRAM L3 cache built into it, dramatically improving performance for many applications. Power7 chip also supports synchronous multi-threading (Simultaneous MultiThreading; SMT), providing four threads per core, up to 32 tasks simultaneously.
The Power7 + shrank to 32 nanometers and IBM was able to lift L3 caches from 32MB in Power7 to 80MB and clock speeds slightly higher.
In 2014 IBM introduced the Power8 reduced to 22 nm process, the chip can accommodate 4.2 billion transistors. So up to 12 cores, L3 cache up to 96MB, and Power8 chip SMT increased to 8 threads per core.
According to OpenPower's High-Performance Computing (HPC) roadmap, Power9 will be available soon, with the interim Power8 chip expected to support NVIDIA's NVLink technology in 2016 to help tightly interface GPUs and CPUs for more efficient mixing (Hybrid) operation.
IBM and its OpenPower partners have targeted R & D plans for the Power10 and even Power11 chips by 2020. But it all depends on whether the 7nm process can be commercialized and mass-produced at GlobalFoundries' fabs in a time-and cost-effective manner.
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